Design Considerations for High Resolution Pipeline ADCs in Digital CMOS Technology
نویسندگان
چکیده
The trade-offs between bandwidth, resolution and power in high dynamic range pipeline analog-to-digital converters are studied when a pure digital CMOS technology is considered. Calibration techniques are presented to achieve the required resolution, and the design optimization methodology of the relevant pipeline building blocks are discussed. An example of a 15-b 10Ms/s analog-to-digital pipeline converter implemented in a 0.35μm digital CMOS technology is presented.
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تاریخ انتشار 2001